As standards for high-speed memory interfaces, the JEDEC (Joint Electron Device Engineering Council) standards (JESD79-3E) for DDR3 (Double-Data-Rate 3) interface, for example, have been known. Such interfaces are standardized so that the transmitting impedance of an output driver (hereinafter referred to as transmitter) and the terminating impedance of a receiver may each be equal to a multiple (or a submultiple) of a fixed resistance value as a reference value.
Where an interface is implemented using a semiconductor, the transmitting impedance or terminating impedance of the interface greatly varies depending on manufacturing (process) variations, power supply voltage during use, and temperature changes. Thus, it has been conventionally known to adjust the impedances of an interface circuit by using, as a reference value, the resistance value of a reference resistor connected externally to the semiconductors.    Japanese Laid-open Patent Publication No. 2008-60629    Japanese Laid-open Patent Publication No. 2006-66833
Meanwhile, where the transmitting impedance of the transmitter and the terminating impedance of the receiver are to be set to respective different values in order to improve the transmission waveform or the like, for example, the transmitter and the receiver may each be provided with an impedance adjustment circuit and an external reference resistor so that their impedances can be set to different values.
In this case, however, a problem arises in that the size of circuitry increases.